1. Field of the Invention
The present invention relates to a process for forming a trench isolation structure for semiconductor devices in an integrated circuit, and in particular, to a process for forming a trench isolation structure wherein shallow trenches overlapping deep trenches are formed without creating defects in the deep trench sidewalls.
2. Description of the Related Art
In semiconductor processing, a typical process requirement is to create trench isolation structures within a semiconductor workpiece. These trench isolation structures are typically filled with dielectric material and electrically isolate semiconductor devices formed in the workpiece from the effects of adjacent active devices.
FIG. 1 shows a cross-sectional view of a conventional trench isolation structure. Trench isolation structure 100 is formed in semiconductor workpiece 102 between first active device 104 and second active device 106. Trench isolation structure 100 includes a shallow component 100a and a deep component 100b. Shallow component 100a typically extends from the surface of the semiconductor workpiece to a depth of between about 0.25 .mu.m and 2.0 .mu.m. Deep component 100b typically extends from the bottom of the shallow component to a depth of between about 1.0 .mu.m and 25 .mu.m in the semiconductor workpiece.
FIGS. 2A-2I show cross-sectional views of the conventional process flow for forming the trench isolation structure of FIG. 1. In FIG. 2A, nitride oxidation mask layer 110 (typically 600-2000 .ANG. thick) is formed over a pad silicon dioxide layer 112 (typically 50-400 .ANG. thick). Pad oxide layer 112 is formed over a semiconductor workpiece composed of single crystal silicon 102. First unexposed positive photoresist layer 114 is then formed over nitride oxidation mask layer 110.
FIG. 2B shows the next step, wherein selected regions 114a of positive photoresist layer 114 are exposed to light 116 through gap 118 in reticle 120. In response to exposure to light 116, unexposed positive photoresist in selected regions 114a undergoes a physical transformation into exposed positive photoresist 122.
FIG. 2C shows the subsequent development step, wherein the wafer is immersed in a solvent in which exposed positive photoresist 122 is soluble, but unexposed positive photoresist 114 is insoluble. As a result of this development step, the exposed positive photoresist dissolves in the solvent and is removed to leave patterned unexposed positive photoresist mask 124 excluding unmasked regions 126.
FIG. 2D shows the next step, wherein nitride oxidation mask layer 110, pad oxide layer 112, and single crystal silicon 102 underlying unmasked region 126 are etched. As a result, deep trench 128 is formed.
FIG. 2E shows the stripping of the first unexposed positive photoresist mask, followed by formation of second unexposed positive photoresist layer 130. As a result of formation of second positive photoresist layer 130, deep trench 128 is filled with unexposed positive photoresist material.
FIG. 2F shows the second photolithography step, wherein second unexposed positive photoresist layer 130 is exposed to light 132 through gap 134 in second reticle 136. In response to exposure to light 132, unexposed positive photoresist 130 in selected regions 138 undergoes a physical transformation into exposed positive photoresist 140. However, because of the depth of deep trench 128, light 132 is prevented from exposing all of the positive photoresist lying within the trench, and bottom positive photoresist portion 130a remains unexposed.
FIG. 2G illustrates the development step, wherein the wafer is immersed in a solvent in which exposed positive photoresist 140 is soluble, but unexposed positive photoresist 130 is insoluble. As a result of this development step, exposed positive photoresist dissolves and is removed to leave patterned unexposed positive photoresist mask 144 revealing unmasked region 146 larger than and including deep trench 128. Unexposed positive photoresist 130a lying at the bottom of deep trench 128 remains in place during this step.
FIG. 2H shows the next step, wherein nitride oxidation mask layer 110, silicon dioxide layer 112, and single crystal silicon 102 underlying unmasked region 146 are exposed to etching. As a result, shallow trench 148 is formed in single crystal silicon 102. FIG. 2H also shows that portion 130a of unexposed positive photoresist lying at the bottom of deep trench 128 interferes with etching during this step, causing etching to occur around periphery of remaining photoresist portion 130a and creating notches 150.
FIG. 2I shows the stripping of the second positive photoresist mask, which also removes the unexposed positive photoresist portion lying at the bottom of deep trench 128. The sidewalls of deep trench 128 and shallow trench 148 are then oxidized to form liner oxide 149. The growth of liner oxide 149 heals defects in single crystal silicon 102 at the trench sidewalls caused by the prior processing steps. Nitride oxidation mask 110 prevents oxidation from occurring outside of trenches 128 and 148 during this step. FIG. 21 also shows the formation of dielectric material 157 (typically CVD silicon dioxide) over the entire surface, including within deep trench 128 and shallow trench 148.
Finally, FIG. 2J shows removal of dielectric material 157 outside of trenches 128 and 148 by CMP to form shallow component 100a overlying deep component 100b. Fabrication of the conventional isolation structure is completed by selectively removing nitride oxidation mask layer 110 relative to underlying pad oxide layer 112. Remaining pad oxide 112 is thin enough to be easily removed without affecting isolation structure 100.
While satisfactory for some applications, the conventional process flow depicted in FIGS. 2A-2J suffers from certain problems. One particularly serious disadvantage of the conventional process is formation of irregularities on the sidewalls of the deep trench during etching of the shallow trench. These irregularities, such as the notches created in FIG. 2H, are caused by interaction between etchant used to form the shallow trench and unexposed positive photoresist remaining at the bottom of the deep trench following shallow trench photolithography. These deep trench sidewall irregularities can give rise to defects in the single crystal silicon and create breakdown voltage pathways between the active devices and the substrate.
Therefore, there is a need in the art for a process for forming an isolation structure featuring deep and shallow components which creates a shallow trench while avoiding formation of a notch or other irregularity in the sidewall of an already-existing deep trench.